1. Field of the Invention
The invention is generally related to the area of integrated circuits designs. More particularly, the invention is related to designs of high-speed integrated circuits that may include, but not be limited to, analog-to-digital converters (ADC).
2. The Background of Related Art
A simple way to make a high-speed and high resolution ADC is to use a full-flash structure as shown in FIG. 1 in which an 8-bit resolution with an array of 255 comparators is demonstrated. This type of converter includes an array of 2^n−1 comparators with n being the number of bits. The input signal is provided to a sample-and-hold circuit first for handling high input frequency purpose. Each comparator is connected with one input to a reference voltage. A resistor ladder generally generates this reference voltage. The output of the comparators is then fed into an encoding logic that generates the data bits. The advantage of this type of full-flash converter includes its easy design, though its inherent offset compensation is required in order to avoid using large transistors in the comparators for matching reasons. The disadvantage of this type of full-flash converters is evident. If, for example, a precision of 8-bit is needed, then 255 comparators are required, resulting in a large chip area and high power consumption.
The folding and interpolating technique as shown in FIG. 2 has a lower comparator count than the full-flash structure, and thus providing lower power consumption and smaller area potentials. Description of an ADC using the folding and interpolating architecture may be found in ‘An 8-bit Video ADC incorporating Folding and Interpolating Techniques,’ authored by R. J. VAN DE GRIFT, p. 944–953, IEEE Journal of solid-state Circuits, Vol. SC-22, No. 6, December 1987, which is hereby incorporated by reference.
FIG. 2 shows a simplified block diagram of an 8-bit ADC using the folding and interpolating technique. The input voltage is applied to a preprocessing circuit depicted as a ‘folding circuit’ and the output of this folding circuit is coupled to a 5-bit fine ADC. The input signal is also directly coupled to a 3-bit coarse ADC. The operation of the folding circuit is illustrated in FIG. 3, where the transfer function of the folding circuit is shown. The ‘zig-zag’ shaped transfer curve covers the entire range of the input Vin (normalized for illustration), and the output voltage of the folding circuit needs to be converted to only 32 levels corresponding to the five least significant bits (LSB's) of the ADC output code. In order to distinguish the eight possible input voltages that correspond to the same folding signal output, the 3-bit coarse ADC is required to generate the three most significant bits (MSB's) of the ADC. The total comparator count for this folding converter is 32 (fine)+8 (coarse)=40, which is much less than 255 comparators for the full-flash structure. It is noted that the three most significant bits and the five least significant bits are generated synchronously, and thus, a sample-and-hold function is basically not required. The throughput of a folding ADC is equal to that of a full-flash structure. The transfer of the folding circuit in FIG. 3 is called ‘8-times-folding’ because, for each folding output, there are eight possible input voltages.
A more detailed folding amplifier and resistor-interpolating ADC concept is illustrated in FIG. 4. The detailed function description can be found from U.S. Pat. No. 4,831,379 (Pat. No. '379) issued to Tudy L.van de Plassche, which is incorporated herein by reference. Although the holding amplifier reduces the comparator counter, the number of comparators required is still large. The principle of the interpolating technique after a folding amplifier is to reduce the number of comparators by simply omitting one out of every two comparators and recovering a missing signal by interpolation between two output signals. The interpolation can be implemented readily by inserting a resistive interpolation ladder containing two resistors between the outputs of the two comparators. At the taps of these resistors, the missing signal can be accurately reconstructed.
U.S. Pat. No. 4,897,656 (Pat. No. '656) issued to Rudy L. van de Plassche provides a description of a similar ADC architecture with a delay network that compensates a delay experienced in Pat. No. '379. The delay network is formed with two or more additional pairs of impedance elements that are used in supplying interpolation output signals at multiple pairs of corresponding interpolation output points. Nevertheless, the delay network still includes a fairly large number of impedance elements.
It is desirable to provide a high-speed ADC architecture with a least number of components without compromising the performance thereof.